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Young companies
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Ranked by keyword. Search by meaning is busy right now.
DFT Design Engineer
Cadence
Austin, United States
Mid-level
25 Aug 2026
New on Evolc
Salary transparent
Intern SSG
Cadence
Cork, Ireland
Intern
Internship
7 weeks ago
New on Evolc
Salary transparent
Lead Application Engineer
Cadence
Feldkirchen, Germany
On-site
Lead
7 weeks ago
New on Evolc
Salary transparent
Principal Design Engineer
Cadence
Cork, Ireland
Lead
13 Aug 2026
New on Evolc
Salary transparent
CMOS SerDes or High-speed I/O, Lead Analog IC Design Engineer
Cadence
San Jose, United States
Lead
2 weeks ago
New on Evolc
Salary transparent
$119,000–221,000 / year
Chip Lead / Physical Design Director
Cadence
Austin, United States
Director
2 weeks ago
New on Evolc
Salary transparent
Application Engineer II: Analog IC Design and Simulation
Cadence
Belo Horizonte, Brazil
On-site
Mid-level
13 Aug 2026
New on Evolc
Salary transparent
RTL2GDS IC Sr. Principal Design Engineer
Cadence
San Jose, United States
Senior
2 weeks ago
New on Evolc
Salary transparent
$161,000–299,000 / year
RTL-to-GDS implementation, Senior Principal Solutions Engineer
Cadence
Austin, United States
Senior
7 days ago
New on Evolc
Salary transparent
Sr. Principal SW Engineer, 3DIC P&R & AI-driven EDA Automation
Cadence
San Jose, United States
Senior
31 Aug 2026
New on Evolc
Salary transparent
$154,000–286,000 / year
RTL2GDS, Product Engineering Architect
Cadence
San Jose, United States
Senior
4 days ago
New on Evolc
Salary transparent
$178,500–331,500 / year
Sr. Principal IC Digital Flow AE
Cadence
San Jose, United States
Senior
4 days ago
New on Evolc
Salary transparent
$148,400–275,600 / year
EDA/CAD Engineer
Kandou AI
Saint-Sulpice, Hyderabad +3
Hybrid
Senior
7 days ago
New on Evolc
Remote-friendly
Digital ASIC Design Engineer
AttoTude
Nuremberg, Germany
Senior
4 weeks ago
CST Application Engineer Intern - Physical Systems
Cadence
San Jose, United States
On-site
Intern
4 weeks ago
New on Evolc
Salary transparent
Software Engineer II: AI Inhouse Adoption
Cadence
Belo Horizonte, Brazil
On-site
Mid-level
5 weeks ago
New on Evolc
Salary transparent
Digital Electronics Principal Verification Engineer
Cadence
Edinburgh, United Kingdom
On-site
Lead
2 weeks ago
New on Evolc
Salary transparent
DSP Hardware Design Engineer
Cadence
San Jose, United States
Senior
26 Aug 2026
New on Evolc
Salary transparent
$136,500–253,500 / year
N
Stage ingénieur : Conception circuits analogiques: Etude du buffer pour une référence de tension ultra précise et invariable dans le temps (F/M)
Nxp
Toulouse, France
Intern
5 weeks ago
New on Evolc
Principal Design Engineer
Cadence
Austin, United States
Senior
8 weeks ago
New on Evolc
Salary transparent
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